The present invention relates to a chip design, and more particularly, to a wafer-level package with at least one input/output port connected to at least one management bus.
When a chip function of a target chip is achieved using a large-sized die, the fabrication of large-sized dies on a wafer will suffer from low yield and high cost. Given the same die area, the yield of one large die is lower than the yield of multiple small dies. More specifically, assuming that distribution of defects on a wafer is the same, a die yield of one large-sized die fabricated on the wafer is lower than a die yield of multiple small-sized dies which have the same area fabricated on the same wafer. However, splitting one large die into multiple smaller dies may bring some overhead. For example, a large number of signals will be introduced to achieve communications between different small-sized dies assembled in the same package. Further, a communication channel between two small-sized dies is required to undergo a calibration procedure before the actual data transaction can be carried out through the communication channel. Thus, there is a need for an innovative design which can achieve calibration of a communication channel between two dies assembled in the same package.